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Refereed Papers at Conferences

  1. Takahiro Yamamoto, Ittetsu Taniguchi, Hiroyuki Tomiyama, Shigeru Yamashita, Yuko Hara-Azumi, "A Systematic Methodology for Design and Analysis of Approximate Array Multipliers," In Proc. of Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 352-354, Jeju, Korea, October 2016.
  2. Yang Liu, Lin Meng, Ittetsu Taniguchi, Hiroyuki Tomiyama, "A Branch-and-Bound Algorithm for Scheduling of Data-Parallel Tasks," In Proc. of Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), pp. 96-100, Kyoto, October 2016.
  3. Yining Xu, Ittetsu Taniguchi, Hiroyuki Tomiyama, "Deadline-Constrained Static Mapping of Parallelizable Tasks on Manycore Architectures," In Proc. of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), pp. 33-36, Naha, July 2016.
  4. Shunsuke Takai, Ittetsu Taniguchi, Hiroyuki Tomiyama, Sri Parameswaran, "An OpenCL Framework for FPGA-based Heterogeneous Multicore Architecture," In Proc. of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), pp. 443-444, Naha, July 2016.
  5. Kana Shimada, Shogo Kitano, Ittetsu Taniguchi, Hiroyuki Tomiyama, "ILP-based Scheduling for Malleable Parallel Tasks," In Proc. of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), pp. 445-446, Naha, July 2016.
  6. Shunsuke Negoro, Ittetsu Taniguchi, Hiroyuki Tomiyama, "Fundamental Analysis of Low Energy Path Routing for Delivery Quadcopters," In Proc. of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), pp. 595-596, Naha, July 2016.
  7. Muneyuki Takenae, Ittetsu Taniguchi, Hiroyuki Tomiyama, "A Case Study on Exploration of FPGA-based Multicore/Manycore Architectures," In Proc. of International Symposium on Low-Power and High-Speed Chips (COOL Chips), Poster presentation, 2 pages, Yokohama, April 2016.
  8. Naohisa Hojo, Ittetsu Taniguchi, Hiroyuki Tomiyama, "Comparison of Thread Execution Methods for GPU-oriented OpenCL Programs on Multicore Processors," In Proc. of Embedded Operating Systems Workshop (EWiLi), Poster presentation, 2 pages, Amsterdam, Netherlands, Oct. 2015.
  9. Muneyuki Takenae, Ittetsu Taniguchi, Hiroyuki Tomiyama, "Design and Implementation of Hierarchical 32-Core Architecture for FPGA-based Embedded Systems," In Proc. of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), pp. 346-348, Seoul, Korea, June-July 2015.
  10. Yohei Onishi, Ittetsu Taniguchi, Hiroyuki Tomiyama, "Revisiting Function Inlining in FPGA High-Level Synthesis," In Proc. of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), pp. 349-351, Seoul, Korea, June-July 2015.
  11. Naohisa Hojo, Ittetsu Taniguchi, Hiroyuki Tomiyama, "Efficient Execution of OpenCL-based GPU Programs on Multicore Processors," In Proc. of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), pp. 352-354, Seoul, Korea, June-July 2015.
  12. Shunsuke Takai, Naoki Nishiyama, Ittetsu Taniguchi, Hiroyuki Tomiyama, "A Lightweight OpenCL Framework for Embedded Multicore Processors," In Proc. of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), Best paper award, pp. 355-357, Seoul, Korea, June-July 2015.
  13. Yining Xu, Junya Kaida, Yang Liu, Ittetsu Taniguchi, Hiroyuki Tomiyama, "Static Task Mapping for Non-Hierarchical Manycore SoCs," In Proc. of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), pp. 519-521, Seoul, Korea, June-July 2015.
  14. Yusuke Fukutsuka, Yosuke Kurimoto, Ittetsu Taniguchi, Hiroyuki Tomiyama, "A Flexible Simulation Framework for Network-on-Chip with QEMU and SystemC," In Proc. of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), pp. 661-663, Seoul, Korea, June-July 2015.
  15. Naoya Ito, Nagisa Ishiura, Hiroyuki Tomiyama, Hiroyuki Kanbara, "High-Level Synthesis from Programs with External Interrupt Handling," In Proc. of Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), pp. 10-15, Yilan, Taiwan, Mar. 2015.
  16. Stefan Hadjis, Andrew Canis, Ryoya Sobue, Yuko Hara-Azumi, Hiroyuki Tomiyama, and Jason Anderson, "Profiling-Driven Multi-Cycling in FPGA High-Level Synthesis," In Proc. of Design, Automation & Test in Europe (DATE), pp. 31-36, Grenoble, France, March 2015.
  17. Yang Liu, Lin Meng, Ittetsu Taniguchi and Hiroyuki Tomiyama, "A Dual-Mode Scheduling Algorithm for Task Graphs with Data Parallelism," In Proc. of Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 371-374, Ishigaki, Japan, November 2014.
  18. Tran Van Dung, Ittetsu Taniguchi and Hiroyuki Tomiyama, "Cache Simulation for Instruction Set Simulator QEMU," In Proc. of International Workshop on Software Defined Sensor Networks (SDSN), World Ubiquitous Science Congress (U-Science), pp. 441-446, Dalian, China, August 2014.
  19. Gang Zeng, Yutaka Matsubara, Hiroyuki Tomiyama and Hiroaki Takada, "Task Migration for Energy Saving in Real-Time Multiprocessor Systems," In Proc. of International Conference on Embedded Software and Systems (ICESS), pp. 693-700, Paris, France, August 2014.
  20. Yuki Ando, Seiya Shibata, Shinya Honda, Hiroyuki Tomiyama and Hiroaki Takada, "Fast Design-Space Exploration Method for SW/HW Codesign on FPGAs," In Proc. of International Symposium on Field-Programmable Custom Computing Machines (FCCM), Poster presentation, p. 235, Boston, MA, USA, May 2014.
  21. Yang Liu, Ittetsu Taniguchi, Hiroyuki Tomiyama, and Lin Meng, "List Scheduling Strategies for Task Graphs with Data Parallelism," In Proc. of International Symposium on Computing and Networking (CANDAR), pp. 168-172, Matsuyama, Dec. 2013.
  22. Yosuke Kurimoto, Yusuke Fukutsuka, Ittetsu Taniguchi and Hiroyuki Tomiyama, "A Hardware/Software Cosimulator for Network-on-Chip," In Proc. of International SoC Design Conference (ISOCC), pp. 172-175, Busan, Korea, Nov. 2013.
  23. Shunsuke Nakamura, Ittetsu Taniguchi, Hiroyuki Tomiyama, and Masahiro Fukui, "A Basic-Block Level Optimistic Energy Estimation for Power-Gated VLIW Data-Path Model," In Proc. of Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), pp. 354-359, Sapporo, Oct. 2013.
  24. Noriko Etani, Takuji Hieda and Hiroyuki Tomiyama, "Design, Implementation and Evaluation of Built-in Functions on Parallel Programming Model in SMYLE OpenCL," In Proc. of International Symposium on Embedded Multicore SoCs (MCSoC), pp. 113-118, Tokyo, Sep. 2013.
  25. Junya Kaida, Ittetsu Taniguchi, Takuji Hieda and Hiroyuki Tomiyama, "A Static Task Mapping Algorithm with Dynamic Task Switching for Embedded Many-core SoCs," In Proc. of International Symposium on Communications and Information Technologies (ISCIT), pp. 293-297, Samui Island, Thailand, Sep. 2013.
  26. Kohei Aoki, Ittetsu Taniguchi, Hiroyuki Tomiyama and Masahiro Fukui, "GA-based Architecture Exploration Method for Low Energy VLIW Data-Path Model," In Proc. of International Symposium on Communications and Information Technologies (ISCIT), pp. 307-310, Samui Island, Thailand, Sep. 2013.
  27. Shunsuke Nakamura, Kohei Aoki, Mitsuya Uchida, Ittetsu Taniguchi, Hiroyuki Tomiyama, and Masahiro Fukui, "A New Metric for Basic-Block Level Rough Energy Estimation for Power-Gated VLIW Data-Path Model," In Proc. of International Symposium on Communications and Information Technologies (ISCIT), pp. 320-324, Samui Island, Thailand, Sep. 2013.
  28. Tran Van Dung, Ittetsu Taniguchi, Takuji Hieda and Hiroyuki Tomiyama, "Function Profiling for Embedded Software by Utilizing QEMU and Analyzer Tool," In Proc. of International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 1251-1254, Ohio, USA, August 2013.
  29. Yuki Ando, Seiya Shibata, Shinya Honda, Hiroyuki Tomiyama and Hiroaki Takada, "Automated Identification of Performance Bottleneck on Embedded Systems for Design Space Exploration," In Proc. of International Embedded Systems Symposium (IESS), Springer IFIP 403, pp. 171-180, Paderborn, Germany, June 2013.
  30. Ryoya Sobue, Yuko Hara-Azumi, and Hiroyuki Tomiyama, "Partial Controller Retiming in High-Level Synthesis," In Proc. of Electronic System Level Synthesis Conference (ESLsyn), pp. 10-15, Austin, TX, USA, May-June 2013.
  31. Yuko Hara-Azumi and Hiroyuki Tomiyama, "Cost-Efficient Scheduling in High-Level Synthesis for Soft-Error Vulnerability Mitigation," In Proc. of International Symposium on Quality Electronic Design (ISQED), pp. 518-523, Santa Clara, CA, USA, Mar. 2013.
  32. Keita Nakajima, Takuji Hieda, Ittetsu Taniguchi, Hiroyuki Tomiyama, and Hiroaki Takada, "A Fast Network-on-Chip Simulator with QEMU and SystemC," In Proc. of International Workshop on Advances in Networking and Computing (WANC) in conjunction with International Conference on Networking and Computing (ICNC), Best paper award, pp. 298-301, Naha, Okinawa, Dec. 2012.
  33. Mitsuya Uchida, Ittetsu Taniguchi, Hiroyuki Tomiyama, Masahiro Fukui, "Energy-Aware ILP-based Instruction Scheduling for Fine-Grained Power-Gated VLIW Processors," In Proc. of International SoC Design Conference (ISOCC), pp. 139-142, Jeju, Korea, Nov. 2012.
  34. Junya Kaida, Takuji Hieda, Ittetsu Taniguchi, Hiroyuki Tomiyama, Yuko Hara-Azumi, and Koji Inoue, "Task Mapping Techniques for Embedded Many-core SoCs," In Proc. of International SoC Design Conference (ISOCC), pp. 204-207, Jeju, Korea, Nov. 2012.
  35. Yuko Hara-Azumi, Toshinobu Matsuba, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, "Selective Resource Sharing with RT-Level Retiming for Clock Enhancement in High-Level Synthesis," Proc. of International Conference on Embedded Software and Systems (ICESS), pp. 1534-1540, Liverpool, UK, June 2012.
  36. Yuko Hara-Azumi, Hiroyuki Tomiyama, Shigeru Yamashita, Nikil D. Dutt, "High-Level Synthesis Using Partially-Programmable Resources for Yield Improvement," In Proc. of Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), pp. 414-419, Beppu, Mar. 2012.
  37. Yuko Hara-Azumi, Hiroyuki Tomiyama, "Clock-Constrained Simultaneous Allocation and Binding for Multiplexer Optimization in High-Level Synthesis," In Proc. of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 251-256, Sydney, Australia, Jan.-Feb. 2012.
  38. Krzysztof Jozwik, Hiroyuki Tomiyama, Masato Edahiro, Shinya Honda and Hiroaki Takada, "Rainbow - An OS Extension for Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs," In Proc. of International Conference on ReConFigurable Computing and FPGAs (ReConFig), pp. 416-421, Cancun, Mexico, Nov.-Dec. 2011.
  39. Yuki Ando, Seiya Shibata, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada, "Fast Design Space Exploration for Mixed Hardware-Software Embedded Systems," In Proc. of International SoC Design Conference (ISOCC), pp. 92-95, Jeju, Korea, Nov. 2011.
  40. Ittetsu Taniguchi, Mitsuya Uchida, Hiroyuki Tomiyama, Masahiro Fukui, Praveen Raghavan, Francky Catthoor, "An Energy Aware Design Space Exploration for VLIW AGU Model with Fine Grained Power Gating," In Proc. of Euromicro Conference on Digital System Design (DSD), pp. 693-700, Oulu, Finland, Aug. 2011.
  41. Hideki Takase, Gang Zeng, Lovic Gauthier, Hirotaka Kawashima, Noritoshi Atsumi, Tomohiro Tatematsu, Yoshitake Kobayashi, Shunitsu Kohara, Takenori Koshiro, Tohru Ishihara, Hiroyuki Tomiyama and Hiroaki Takada, "An Integrated Optimization Framework for Reducing the Energy Consumption of Embedded Real-Time Applications," In Proc. of International Symposium on Low-Power Electronics and Design (ISLPED), pp. 271-276, Fukuoka, Japan, August 2011.
  42. Kohei Aoki, Ittetsu Taniguchi, Hiroyuki Tomiyama, Masahiro Fukui, "Architecture Optimization based on a Branch-and-Bound Strategy for Low-Energy Embedded VLIW Processors," In Proc. of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), pp. 207-210, Gyeongju, Korea, June 2011.
  43. Mitsuya Uchida, Ittetsu Taniguchi, Hiroyuki Tomiyama, Masahiro Fukui, "Energy-Aware ILP-based Instruction Scheduling for Fine-Grained Power-Gated VLIW Processors," In Proc. of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), pp. 211-214, Gyeongju, Korea, June 2011.
  44. Tomohiro Tatematsu, Hideki Takase, Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada, "Checkpoints Extraction Using Execution Traces for Intra-Task DVFS in Embedded Systems," In Proc. of International Symposium on Electronic Design, Test and Applications (DELTA), pp. 19-24, Queenstown, New Zealand, Jan. 2011.
  45. Lovic Gauthier, Tohru Ishihara, Hideki Takase, Hiroyuki Tomiyama, Hiroaki Takada, "Minimizing Inter-Task Interferences in Scratch-Pad Memory Usage for Reducing the Energy Consumption of Multi-Task Systems," In Proc. of International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), pp. 157-166, Scottsdale, AZ, USA, October 2010.
  46. Lovic Gauthier, Tohru Ishihara, Hideki Takase, Hiroyuki Tomiyama, Hiroaki Takada, "Placing Static and Stack Data into a Scratch-Pad Memory for Reducing the Energy Consumption of Multi-task Applications," In Proc. of Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), Outstanding Paper Award, pp. 7-12, Taipei, Taiwan, Oct. 2010.
  47. Yuko Hara-Azumi, Toshinobu Matsuba, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, "Aggressive Register Unsharing with Selective FU Sharing in High-Level Synthesis," In Proc. of Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), pp. 13-18, Taipei, Taiwan, Oct. 2010.
  48. Krzysztof Jozwik, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, "A Novel Mechanism for Effective Hardware Task Preemption in Dynamically Reconfigurable Systems," In Proc. of International Conference on Field Programmable Logic and Applications (FPL), pp. 352-355, Milano, Italy, August-Sepember 2010.
  49. Yuki Ando, Seiya Shibata, Shinya Honda, Hiroyuki Tomiyama and Hiroaki Takada, "Automatic Communication Synthesis with Hardware Sharing for Design Space Exploration," In Proc. of International Symposium on Circuits and Systems (ISCAS), pp. 1863-1866, Paris, France, May-June 2010.
  50. H. Takase, H. Tomiyama, and H. Takada, "Partitioning and Allocation of Scratch-Pad Memory for Priority-Based Preemptive Multi-Task Systems," In Proc. of Design Automation and Test in Europe (DATE), pp. 1124-1129, Dresden, Germany, Mar. 2010.
  51. T. Matsuba, Y. Hara, H. Tomiyama, S. Honda, and H. Takada, "Aggressive Register Unsharing Based on SSA Transformation for Clock Enhancement in High-Level Synthesis ," In Proc. of International Symposium on Electronic Design, Test and Applications (DELTA), pp. 87-92, Ho Chi Minh, Vietnam, Jan. 2010.
  52. S. Shibata, Y. Ando, S. Honda, H. Tomiyama, and H. Takada, "Automatic Instrumentation of Profilers for FPGA-based Design Space Exploration ," In Proc. of International Conference on Field-Programmable Technology (FPT), pp. 292-295, Sydney, Australia, Dec. 2009.
  53. T. Majima, T. Yokoyama, G. Zeng, T. Kamiyama, H. Tomiyama, and H. Takada, "Modeling Power Consumption of Applications in Wireless Communication Devices Using OS Level Profiles ," In Proc. of International SoC Design Conference (ISOCC), pp. 253-256, Busan, Korea, Nov. 2009.
  54. G. Zeng, T. Yokoyama, H. Tomiyama, and H. Takada, "Practical Energy-Aware Scheduling for Real-Time Multiprocessor Systems ," In Proc. of International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), pp. 383-392, Beijing, China, Aug. 2009.
  55. T. Yokoyama, G. Zeng, H. Tomiyama, H. Takada, "Heuristics for Static Voltage Scheduling Algorithms on Battery-Powered DVS Systems ," In Proc. of International Conference on Embedded Software and Systems (ICESS), pp. 265-272, HangZhou, Zhejiang, China, May 2009.
  56. H. Takase, H. Tomiyama, and H. Takada, "Allocation of Scratch-Pad Memory in Multi-Task Systems ," In Proc. of International Symposium on VLSI Design, Automation and Test (VLSI-DAT), pp. 68-71, Hsinchu, Taiwan, Apr. 2009.
  57. S. Shibata, S. Honda, H. Tomiyama, and H. Takada, "A Case Study on MPEG4 Decoder Design with SystemBuilder ," In Proc. of International Symposium on VLSI Design, Automation and Test (VLSI-DAT), pp. 355-358, Hsinchu, Taiwan, Apr. 2009.
  58. Y. Ando, S. Shibata, S. Honda, H. Tomiyama, and H. Takada, "A Case Study on AES Encryption System Design with SystemBuilder ," In Proc. of Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), pp. 283-288, Naha, Japan, Mar. 2009.
  59. T. Yokoyama, G. Zeng, H. Tomiyama, and H. Takada, "Analyzing and Optimizing Energy Efficiency of Algorithms on DVS Systems: A First Step towards Algorithmic Energy Minimization ," In Proc. of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 727-732, Yokohama, Japan, Jan. 2009.
  60. G. Zeng, H. Tomiyama, H. Takada, and T. Ishihara, "A Generalized Framework for System-Wide Energy Savings in Hard Real-Time Embedded Systems ," In Proc. of International Conference on Embedded and Ubiquitous Computing (EUC), pp. 206-213, Shanghai, China, Dec. 2008.
  61. Y. Hara, H. Tomiyama, S. Honda, H. Takada, and K. Ishii, "Behavioral Partitioning with Exploiting Function-Level Parallelism ," In Proc. of International SoC Design Conference (ISOCC), pp. 121-124, Busan, Korea, Nov. 2008.
  62. H. Takase, H. Tomiyama, G. Zeng, and H. Takada, "Energy Efficiency of Scratch-Pad Memory at 65 nm and Below: An Empirical Study ," In Proc. of International Conference on Embedded Software and Systems (ICESS), pp. 93-97, Chengdu, China, July 2008.
  63. Y. Hara, H. Tomiyama, S. Honda, H. Takada, and K. Ishii, "CHStone: A Benchmark Program Suite for Practical C-Based High-Level Synthesis ," In Proc. of International Symposium on Circuits and Systems (ISCAS), pp. 1192-1195, Seattle, WA, USA, May 2008.
  64. J. Zushi, G. Zeng, H. Tomiyama, H. Takada, and K. Inoue, "Improved Policies for Drowsy Caches in Embedded Processors ," In Proc. of International Symposium on Electronic Design, Test and Applications (DELTA), pp. 362-367, Hong Kong, China, Jan. 2008.
  65. G. Zeng, H. Tomiyama, and H. Takada, "A Software Framework for Energy and Performance Tradeoff in Fixed-Priority Hard Real-Time Embedded Systems ," In Proc. of International Conference on Embedded and Ubiquitous Computing (EUC), Springer Lecture Notes in Computer Science (LNCS) 4808 ", pp. 13-24, Taipei, Taiwan, Dec. 2007.
  66. H. Kanbara, T. Nakatani, N. Umehara, N. Ishiura, and H. Tomiyama, "Speed Improvement of AES Encryption using Hardware Acclererators Synthesized by C Compatible Architecture Prototyper (CCAP) ," In Proc. of Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), pp. 130-134, Sapporo, Japan, Oct. 2007.
  67. M. Nishimura, N. Ishiura, Y. Ishimori, H. Kanbara, and H. Tomiyama, "Calling Software Functions from Hardware Functions in High-Level Synthesizer CCAP ," In Proc. of Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), pp. 357-360, Sapporo, Japan, Oct. 2007.
  68. S. Shibata, S. Honda, Y. Hara, H. Tomiyama, and H. Takada, "Hardware/Software Covalidation with FPGA and RTOS Model ," In Proc. of Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), pp. 488-494, Sapporo, Japan, Oct. 2007.
  69. S. Ding, H. Tomiyama, and H. Takada, "Scheduling Algorithms for I/O Blockings with a Multi-frame Task Model ," In Proc. of International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), pp. 386-393, Daegu, Korea, Aug. 2007.
  70. G. Zeng, H. Tomiyama, and H. Takada, "Power Optimization for Embedded System Idle Time in the Presence of Periodic Interrupt Services ," In Proc. of International Embedded Systems Symposium (IESS), Springer IFIP 231 ", pp. 241-254, Irvine, CA, USA, May-June 2007.
  71. Y. Hara, H. Tomiyama, S. Honda, H. Takada, and K. Ishii, "Behavioral Synthesis of Double-Precision Floating-Point Adders with Function-Level Transformations: A Case Study ," In Proc. of International Conference on Embedded Software and Systems (ICESS), Springer Lecture Notes in Computer Science (LNCS) 4523 ", pp. 261-270, Daegu, Korea, May 2007.
  72. T. Furukawa, S. Honda, H. Tomiyama, and H. Takada, "A Hardware/Software Cosimulator with RTOS Supports for Multiprocessor Embedded Systems ," In Proc. of International Conference on Embedded Software and Systems (ICESS), Springer Lecture Notes in Computer Science (LNCS) 4523 ", pp. 283-294, Daegu, Korea, May 2007.
  73. Y. Hara, H. Tomiyama, S. Honda, H. Takada and K. Ishii, "Complexity-Constrained Partitioning of Sequential Programs for Efficient Behavioral Synthesis ," In Proc. of Great Lakes Symposium on VLSI (GLSVLSI), pp. 365-370, Stresa, Italy, Mar 2007.
  74. M. Yamamoto, S. Honda, H. Takada, K. Agusa, H. Tomiyama, K. Mase, N. Kawaguchi, and N. Kaneko, "An Extension Course for Training Trainers of Embedded Software ," In Proc. of 2nd Workshop on Embedded Systems Education (WESE), pp. 95-102, Seoul, Korea, Oct. 2006.
  75. Y. Hara, H. Tomiyama, S. Honda, and H. Takada, "Function Call Optimization in Behavioral Synthesis ," In Proc. of EUROMICRO Conference on Digital System Design (DSD), pp. 522-529, Cavtat/Dubrovnik, Croatia, Aug. 2006.
  76. H. Minamide, T. Yoshimoto, Y. Takagi, S. Honda, H. Tomiyama, and H. Takada, "Communication Interfaces for System Level Design ," In Proc. of Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), pp. 21-28, Nagoya, Japan, Apr. 2006.
  77. M. Nishimura, K. Nishiguchi, N. Ishiura, H. Kanbara, H. Tomiyama, Y. Takatsukasa, and M. Kotani, "High-Level Synthesis of Variable Accesses and Function Calls in Software Compatible Hardware Synthesizer CCAP ," In Proc. of Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), pp. 29-34, Nagoya, Japan, Apr. 2006.
  78. S. Chikada, S. Honda, H. Tomiyama, and H. Takada, "Cosimulation of ITRON-Based Embedded Software with SystemC ," In Proc. of International High Level Design Validation and Test Workshop (HLDVT), pp. 71-76, Napa, CA, USA, Nov. 2005.
  79. M. Yamamoto, H. Tomiyama, H. Takada, K. Agusa, K. Mase, N. Kawaguchi, S. Honda, and N. Kaneko, "NEXCESS: Nagoya University Extension Courses for Embedded Software Specialists ," In Proc. of 1st Workshop on Embedded Systems Education (WESE), pp. 16-20, Jersey City, NJ, USA, Sep. 2005.
  80. S. Ding, N. Murakami, H. Tomiyama, and H. Takada, "A GA-Based Scheduling Method for FlexRay Systems ," In Proc. of International Conference on Embedded Software (EMSOFT), pp. 110-113, Jersey City, NJ, USA, Sep. 2005.
  81. H. Miyamoto, S. Iiyama, H. Tomiyama, H. Takada, and H. Nakashima, "An Efficient Search Algorithm of Worst-Case Cache Flush Timings ," In Proc. of International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), pp. 45-52, Hong Kong, China, Aug. 2005.
  82. H. Tomiyama, S. Chikada, S. Honda, and H. Takada, "An RTOS-Based Approach to Design and Validation of Embedded Systems ," In Proc. of International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), pp. 185-187, Hsinchu, Taiwan, Apr. 2005.
  83. S. Honda, T. Wakabayashi, H. Tomiyama, and H. Takada, "RTOS-Centric Hardware/Software Cosimulator for Embedded System Design ," In Proc. of International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 158-163, Stockholm, Sweden, Sep. 2004.
  84. H. Tomiyama, H. Takada, and N. Dutt, "Data Organization Exploration for Low-Energy Address Buses ," In Proc. of the First Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia), pp. 128-133, Newport Beach, USA, Oct. 2003.
  85. L. Gauthier, N. Devroye, H. Tomiyama, K. Murakami, "A Front-end for Better Handling of High-level Hardware Descriptions ," In Proc. of 11th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 121-128, Hiroshima, Japan, Apr. 2003.
  86. H. Tomiyama, Y. Cao, U. Mesbah, A. Inoue, E. Fajar, H. Yamashita, and H. Yasuura, "A Framework for Bitwidth Optimization in System-on-Chip Design ," 1st Workshop on Application Specific Processors (WASP), Istanbul, Turkey, Nov. 2002.
  87. Y. Cao, H. Tomiyama, T. Okuma, and H. Yasuura, "Data Memory Design Considering Effective Bitwidth for Low-Energy Embedded Systems ," In Proc. of 15th International Symposium on System Synthesis (ISSS), pp. 201-206, Kyoto, Japan, Oct. 2002.
  88. P. Mishra, N. Dutt, A Nicolau, and H Tomiyama, "Automatic Verification of In-Order Execution in Microprocessors with Fragmented Pipelines and Multicycle Functional Units ," In Proc. of Design Automation and Test in Europe (DATE), pp. 36-43, Paris, France, Mar. 2002.
  89. P. Mishra, H Tomiyama, A Halambi, P. Grun, N. Dutt, and A Nicolau, "Automatic Modeling and Validation of Pipeline Specifications Driven by an Architecture Description Language ," In Proc. of Joint Conference on VLSI Design (VLSI) and Asia and Sout Pacific Design Automation Conference (ASP-DAC), pp. 458-463, Bangalore, India, Jan. 2002.
  90. H. Tomiyama, Y. Cao, and K. Murakami, "Modeling Fixed-Priority Preemptive Multi-Task Systems in SpecC ," In Proc. of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pp. 93-100, Nara, Japan, Oct. 2001.
  91. A. Datta, S. Choudhury, A. Basu, H. Tomiyama, and N. Dutt, "Satisfying Timing Constraints of Preemptive Real-Time Tasks through Task Layout Technique ," In Proc. 14th International Conference on VLSI Design, pp. 97-102, Bangalore, India, Jan. 2001.
  92. H. Tomiyama, T. Yoshino, and N. Dutt, "Verification of In-Order Execution in Pipelined Processors ," In Proc. of 5th International High Level Design Validation and Test Workshop (HLDVT), pp. 40-44, Berkeley, USA, Nov. 2000.
  93. H. Tomiyama and N. Dutt, "Program Path Analysis to Bound Cache-Related Preemption Delay in Preemptive Real-Time Systems ," In Proc. of 8th International Workshop on Hardware/Software Codesign (CODES), pp. 67-71, San Diego, USA, May 2000.
  94. A. Datta, S. Choudhury, A. Basu, H. Tomiyama, and N. Dutt, "Task Layout Generation to Minimize Cache Miss Penalty for Preemptive Real Time Tasks: An ILP Approach ," In Proc. of 9th Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pp. 202-208, Kyoto, Japan, Apr. 2000.
  95. H. Tomiyama, A. Halambi, P. Grun, N. Dutt, and A. Nicolau, "Modeling and Verification of Processor Pipelines in SOC Design Exploration ," In Proc. of 4rd International High Level Design Validation and Test Workshop (HLDVT), pp. 10-16, San Diego, USA, Nov. 1999.
  96. H. Tomiyama, A. Inoue, and H. Yasuura, "Statistical Performance-Driven Module Binding in High-Level Synthesis ," In Proc. of 11th International Symposium on System Synthesis (ISSS), pp. 66-71, Hsinchu, Taiwan, Dec. 1998.
  97. T. Okuma, H. Tomiyama, A. Inoue, F. N. Eko, and H. Yasuura, "Instruction Encoding Techniques for Area Minimization of Instruction ROM ," In Proc. of 11th International Symposium on System Synthesis (ISSS), pp. 125-130, Hsinchu, Taiwan, Dec. 1998.
  98. H. Date, H. Tomiyama, and H. Yasuura, "Criteria of Performance Verification and Test for Core-Based LSIs ," In Proc. of 3rd International High Level Design Validation and Test Workshop (HLDVT), pp. 116-119, La Jolla, USA, Nov. 1998.
  99. H. Yamashita, H. Tomiyama, A. Inoue, F. N. Eko, T. Okuma, and H. Yasuura, "Variable Size Analysis for Datapath Width Optimization ," In Proc. of Asia Pacific Conference on Hardware Description Languages (APCHDL), pp. 69-74, Seoul, Korea, July 1998.
  100. A. Inoue, H. Tomiyama, F. N. Eko, H. Kanbara, and H. Yasuura, "A Programming Language for Processor Based Embedded Systems ," In Proc. of Asia Pacific Conference on Hardware Description Languages (APCHDL), pp. 89-94, Seoul, Korea, July 1998.
  101. F. N. Eko, A. Inoue, H. Tomiyama, and H. Yasuura, "A Soft-Core Processor Architecture for Embedded System Design ," In Proc. of Asia Pacific Conference on Hardware Description Languages (APCHDL), pp. 154-159, Seoul, Korea, July 1998.
  102. H. Tomiyama, T. Ishihara, A. Inoue, and H. Yasuura, "Instruction Scheduling for Power Reduction in Processor-Based System Design ," In Proc. of Design Automation and Test in Europe (DATE), pp. 855-860, Paris, France, Feb. 1998.
  103. H. Tomiyama and H. Yasuura, "Module Selection Using Manufacturing Information ," In Proc. of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 275-281, Yokohama, Japan, Feb. 1998.
  104. B. Shackleford, M. Yasuda, E. Okushi, H. Koizumi, H. Tomiyama, and H. Yasuura, "Memory-CPU Size Optimization for Embedded System Designs ," In Proc. of 34th Design Automation Conference (DAC), pp. 246-251, Anaheim, USA, June 1997.
  105. B. Shackleford, M. Yasuda, E. Okushi, H. Koizumi, H. Tomiyama, and H. Yasuura, "The Satsuki Integrated Processor Synthesis and Compiler Generation System ," In Proc. of 6th Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pp. 135-142, Fukuoka, Japan, Nov. 1996.
  106. H. Tomiyama and H. Yasuura, "Size-Constrained Code Placement for Cache Miss Rate Reduction ," In Proc. of 9th International Symposium on System Synthesis (ISSS), pp. 96-101, La Jolla, USA, Nov. 1996.
  107. H. Tomiyama and H. Yasuura, "Optimal Code Placement of Embedded Software for Instruction Caches ," In Proc. of European Design and Test Conference (ED&TC), pp. 96-101, Paris, France, Mar. 1996.
  108. H. Yasuura, S. Nakamura, H. Tomiyama, and H. Akaboshi, "Hardware-Software Codesign with a Soft-Core Processor ," In Proc. of 5th Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pp. 79-84, Nara, Japan, Aug. 1995.
  109. H. Tomiyama, H. Akaboshi, and H. Yasuura, "Compiler Generator for Hardware/Software Codesign ," In Proc. of 2nd Asia Pacific Conference on Hardware Description Languages (APCHDL), pp. 267-270, Toyohashi, Japan, Oct. 1994.
  110. H. Akaboshi, H. Tomiyama, and H. Yasuura, "Compiler Generation from Hardware Description Language ," In Proc. of 1st Asian Pacific Conference on Hardware Description Languages, Standards & Applications (APCHDLSA), pp. 76-78, Brisbane, Australia, Dec. 1993.