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Journals and Magazines

Journals

  1. Takahiro Yamamoto, Ittetsu Taniguchi, Hiroyuki Tomiyama, Shigeru Yamashita, Yuko Hara-Azumi, "A Systematic Methodology for Design and Worst-Case Error Analysis of Approximate Array Multipliers," IEICE Trans. on Fundamentals, vol. E100-A, no. 7, pp. 1496-1499, July 2017. [Download]
  2. Yining Xu, Ittetsu Taniguchi, Hiroyuki Tomiyama, "Static Mapping of Parallelizable Tasks under Deadline Constraints," IEICE Trans. on Fundamentals, vol. E100-A, no. 7, pp. 1500-1502, July 2017. [Download]
  3. Kana Shimada, Shogo Kitano, Ittetsu Taniguchi, Hiroyuki Tomiyama, "ILP-based Scheduling for Parallelizable Tasks," IEICE Trans. on Fundamentals, vol. E100-A, no. 7, pp. 1503-1505, July 2017. [Download]
  4. Yang Liu, Lin Meng, Ittetsu Taniguchi, and Hiroyuki Tomiyama, "A Dual-Mode Scheduling Approach for Task Graphs with Data Parallelism," International Journal of Embedded Systems, Inderscience Publishers, vol. 9, no. 2, pp. 147-156, April 2017. [Download]
  5. Yining Xu, Yang Liu, Junya Kaida, Ittetsu Taniguchi, and Hiroyuki Tomiyama, "Static Mapping of Multiple Parallel Applications on Non-Hierarchical Manycore Embedded Systems," IEICE Trans. on Fundamentals, vol. E99-A, no. 7, pp. 1417-1419, July 2016. [Download]
  6. Gang Zeng, Yutaka Matsubara, Hiroyuki Tomiyama, and Hiroaki Takada, "Energy-Aware Task Migration for Multiprocessor Real-Time Systems," Future Generation Computer Systems, Elsevier, vol. 56, pp. 220-228, March 2016. [Download]
  7. Tran Van Dung, Ittetsu Taniguchi, Takuji Hieda and Hiroyuki Tomiyama, "Function-Level Profiling for Embedded Software with QEMU," International Journal of Embedded Systems, Inderscience Publishers, vol. 7, no. 2, pp. 170-179, June 2015. [Download]
  8. Hideki Takase, Gang Zeng, Lovic Gauthier, Hirotaka Kawashima, Noritoshi Atsumi, Tomohiro Tatematsu, Yoshitake Kobayashi, Takenori Koshiro, Tohru Ishihara, Hiroyuki Tomiyama and Hiroaki Takada "An Integrated Framework for Energy Optimization of Embedded Real-Time Applications," IEICE Trans. on Fundamentals, vol. E97-A, no. 12, pp. 2477-2487, Dec. 2014. [Download]
  9. Ittetsu Taniguchi, Junya Kaida, Takuji Hieda, Yuko Hara-Azumi, and Hiroyuki Tomiyama, "Static Mapping with Dynamic Switching of Multiple Data-Parallel Applications on Embedded Many-core SoCs," IEICE Trans. on Information and Systems, vol. E97-D, no. 11, pp. 2827-2834, Nov. 2014. [Download]
  10. Yang Liu, Lin Meng, Ittetsu Taniguchi and Hiroyuki Tomiyama, "Novel List Scheduling Strategies for Data Parallelism Task Graphs," International Journal on Networking and Computing, vol. 4, no. 2, pp. 279-290, July 2014. [Free Download]
  11. Yuki Ando, Seiya Shibata, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada, "SEEDS: System-level Design Environment for Embedded Systems (in Japanese)," IEICE Transactions on Information and Systems, vol. J97-D, no. 3, pp. 450-460, March 2014.
  12. Yuko Hara-Azumi, Toshinobu Matsuba, Hiroyuki Tomiyama, Shinya Honda and Hiroaki Takada, "Impact of Resource Sharing and Register Retiming on Area and Performance of FPGA-based Designs," IPSJ Transactions on System LSI Design Methodology, vol. 7, pp. 37-45, Feb. 2014. [Free Download]
  13. Ittetsu Taniguchi, Kohei Aoki, Hiroyuki Tomiyama, Praveen Raghavan, Francky Catthoor, Masahiro Fukui, "Fast and Accurate Architecture Exploration for High Performance and Low Energy VLIW Data-Path," IEICE Transactions on Fundamentals, vol. E97-A, no. 2, pp. 606-615, Feb. 2014. [Download]
  14. Junya Kaida, Yuko Hara-Azumi, Takuji Hieda, Ittetsu Taniguchi, Hiroyuki Tomiyama, and Koji Inoue, "Static Mapping of Multiple Data-Parallel Applications on Embedded Many-core SoCs,IEICE Transactions on Information and Systems, vol. E96-D, no. 10, pp. 2268-2271, Oct. 2013. [Download]
  15. Krzysztof Jozwik, Shinya Honda, Masato Edahiro, Hiroyuki Tomiyama and Hiroaki Takada, "Rainbow: An Operating System for Software-Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs," International Journal of Reconfigurable Computing, vol. 2013, Article ID 789134, 40 pages, 2013. [Free Download]
  16. Yuko Hara-Azumi, Toshinobu Matsuba, Hiroyuki Tomiyama, Shinya Honda and Hiroaki Takada, "Quantitative Evaluation of Resource Sharing in High-Level Synthesis Using Realistic Benchmarks," IPSJ Transactions on System LSI Design Methodology, vol. 6, pp. 122-126, Aug. 2013. [Free Download]
  17. Keita Nakajima, Shuto Kurebayashi, Yusuke Fukutsuka, Takuji Hieda, Ittetsu Taniguchi, Hiroyuki Tomiyama, and Hiroaki Takada, "Naxim: A Fast and Retargetable Network-on-Chip Simulator with QEMU and SystemC," International Journal on Networking and Computing, vol. 3, no. 2, pp. 217-227, July 2013. [Free Download]
  18. Hirofumi Kawauchi, Ittetsu Taniguchi, Hiroyuki Tomiyama, and Masahiro Fukui, "Accurate and Efficient RTL Power Estimation based on Power Contour Model," Electrical Engineering in Japan, vol. 182, no. 3, pp. 48-56, Feb. 2013. [Download]
  19. Krzysztof Jozwik, Hiroyuki Tomiyama, Masato Edahiro, Shinya Honda and Hiroaki Takada, "Comparison of Preemption Schemes for Partially Reconfigurable FPGAs," IEEE Embedded Systems Letters, vol. 4, no. 2, pp. 45-48, June 2012. [Download]
  20. Seiya Shibata, Yuki Ando, Shinya Honda, Hiroyuki Tomiyama and Hiroaki Takada, "A Fast Performance Estimation Framework for System-Level Design Space Exploration," IPSJ Transactions on System LSI Design Methodology, vol. 5, pp. 44-54, Feb. 2012. [Free Download]
  21. Krzysztof Jozwik, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, "A Novel Framework for Effective Preemptive Hardware Multitasking on FPGAs," IEICE Transactions on Information and Systems, vol. E95-D, no. 2, pp. 345-353, Feb. 2012. [Download]
  22. Tomohiro Tatematsu, Hideki Takase, Gang Zeng, Hirotaka Kawashima, Hiroyuki Tomiyama, Hiroaki Takada, "Execution Trace Based Checkpoint Extraction for Intra-Task DVFS in Embedded Systems (in Japanese)," IPSJ Journal, vol. 52, no. 12, pp. 3729-3744, Dec. 2011. [Download]
  23. Hirofumi Kawauchi, Ittetsu Taniguchi, Hiroyuki Tomiyama, and Masahiro Fukui, "An Accurate and Efficient RTL Power Estimation based on Power Contour Model (in Japanese)," IEEJ Transactions on Electronics, Information and Systems, vol. 131, no. 11, pp.1907-1914, Nov. 2011. [Download]
  24. Hideki Takase, Hiroyuki Tomiyama and Hiroaki Takada, "Partitioning and Allocation of Scratch-Pad Memory for Energy Minimization of Priority-Based Preemptive Multi-Task Systems," IEICE Transactions on Fundamentals, vol. E94-A, no. 10, pp. 1954-1964, Oct. 2011. [Download]
  25. Seiya Shibata, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada, "SystemBuilder-MP: System-Level Multiprocessor Design Toolset (in Japanese)," IEICE Transactions on Information and Systems, vol. J94-D, no. 4, pp. 657-670, Apr. 2011. [Download]
  26. Yuki Ando, Seiya Shibata, Shinya Honda, Hiroyuki Tomiyama and Hiroaki Takada, "Automatic Communication Synthesis with Hardware Sharing for Multi-Processor SoC Design," IEICE Transactions on Fundamentals, vol. E93-A, no. 12, pp. 2509-2516, Dec. 2010. [Download]
  27. Takuya Azumi, Takashi Furukawa, Hiroshi Aiba, Seiya Shibata, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada, "Open Source Simulator for Embedded System Extended Multiprocessor (in Japanese)," JSSST Computer Software, vol. 27, no. 4, pp. 24-42, Nov. 2010. [Free Download]
  28. Tetsuo Yokoyama, Gang Zeng, Hiroyuki Tomiyama, and Hiroaki Takada, "Static Task Scheduling Algorithms Based on Greedy Heuristics for Battery-Powered DVS Systems," IEICE Transactions on Information and Systems, vol. E93-D, no. 10, pp. 2737-2746, Oct. 2010. [Download]
  29. Seiya Shibata, Yuki Ando, Shinya Honda, Hiroyuki Tomiyama and Hiroaki Takada, "Efficient Design Space Exploration at System Level with Automatic Profiler Instrumentation," IPSJ Transactions on System LSI Design Methodology, vol. 3, pp. 179-193, Aug. 2010. [Free Download]
  30. Y. Hara, H. Tomiyama, S. Honda, and H. Takada, "Partitioning of Behavioral Descriptions Exploiting Function-Level Parallelism," IEICE Trans. Fundamentals, vol. E93-A, no. 2, pp. 488-499, Feb. 2010. [Download]
  31. Y. Hara, H. Tomiyama, S. Honda, and H. Takada, "Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-Based High-Level Synthesis," IPSJ Journal of Information Processing (JIP), vol. 17, pp. 242-254, Oct. 2009. [Free Download]
  32. G. Zeng, H. Tomiyama, and H. Takada, "A Generalized Framework for Energy Savings in Hard Real-Time Embedded Systems," IPSJ Trans. System LSI Design Methodology (TSLDM), vol. 2, pp.167-179, Aug. 2009. [Free Download]
  33. H. Takase, H. Tomiyama, and H. Takada, "Partitioning and Allocation of Scratch-Pad Memory in Priority-Based Multi-Task Systems," IPSJ Trans. System LSI Design Methodology (TSLDM), vol. 2, pp.180-188, Aug. 2009. [Free Download]
  34. S. Ding, H. Tomiyama, and H. Takada, "Effective Scheduling Algorithms for I/O Blocking with a Multi-Frame Task Model," IEICE Trans. Information and Systems, vol. E92-D, no. 7, pp. 1412-1420, July 2009. [Download]
  35. T. Yokoyama, K. Imai, G. Zeng, H. Tomiyama, H. Takada, and S. Yuen, "Energy Efficient Functional Programing on DVS Systems by Varying Evaluation Strategies (in Japanese)," IPSJ Trans. Programming, vol. 2, no. 2, pp. 54-69, Mar. 2009. [Free Download]
  36. H. Takase, H. Tomiyama, G. Zeng, and H. Takada, "Energy Efficiency of Scratch-Pad Memory in Deep Submicron Domains: An Empirical Study," IEICE Electronics Express, vol. 5, no. 23, pp. 1010-1016, Dec. 2008. [Free Download]
  37. M. Nishimura, N. Ishiura, Y. Ishimori, H. Kanbara, and H. Tomiyama, "High-Level Synthesis of Software Function Calls," IEICE Trans. Fundamentals, vol. E91-A, no. 12, pp. 3556-3558, Dec. 2008. [Download]
  38. Y. Matsubara, S. Honda, H. Tomiyama, and H. Takada, "A Flexible Scheduling Framework for Integration of Real-Time Applications (in Japanese)," IPSJ Journal, vol. 49, no. 10, pp. 3508-3519, Oct. 2008. [Download]
  39. G. Zeng, H. Tomiyama, and H. Takada, "Dynamic Power Management for Embedded System Idle State in the Presence of Periodic Interrupt Services," IPSJ Trans. System LSI Design Methodology (TSLDM), pp. 48-57, vol. 1, Aug. 2008. [Free Download]
  40. S. Shibata, S. Honda, Y. Hara, H. Tomiyama, and H. Takada, "Embedded System Covalidation with RTOS Model and FPGA," IPSJ Trans. System LSI Design Methodology (TSLDM), pp. 126-130, vol. 1, Aug. 2008. [Free Download]
  41. S. Ding, H. Tomiyama, and H. Takada, "An Effective GA-Based Scheduling Algorithm for FlexRay Systems," IEICE Trans. Information and Systems, vol. E91-D, no. 8, pp. 2115-2123, Aug. 2008. [Download]
  42. Y. Hara, H. Tomiyama, S. Honda, H. Takada, and K. Ishii, "Function-Level Partitioning of Sequential Programs for Efficient Behavioral Synthesis," IEICE Trans. Fundamentals, vol. E90-A, no. 12, pp. 2853-2862, Dec. 2007. [Download]
  43. Y. Hara, H. Tomiyama, S. Honda, and H. Takada, "Function Call Optimization for Efficient Behavioral Synthesis," IEICE Trans. Fundamentals, vol. E90-A, no. 9, pp. 2032-2036, Sep. 2007. [Download]
  44. Y. Matsubara, S. Honda, H. Tomiyama, and H. Takada, "Real-Time Scheduling Algorithm for Temporal Protection (in Japanese)," IPSJ Trans. Advanced Computing Systems, vol. 48, no. SIG8 (ACS18), pp. 192-202, May 2007. [Free Download]
  45. N. Murakami, H. Tomiyama, and H. Takada, "A Static Scheduling Method for Distributed Automotive Control Systems (in Japanese)," IPSJ Trans. Advanced Computing Systems, vol. 48, no. SIG8 (ACS18), pp. 203-215, May 2007. [Free Download]
  46. M. Yamamoto, S. Honda, H. Takada, K. Agusa, H. Tomiyama, K. Mase, N. Kawaguchi, and N. Kaneko, "Practice and Analysis of an Extension Course for Training Trainers of Embedded Software," ACM SIGBED Review, vol. 4, no. 1, pp. 73-81, Jan. 2007. [Download]
  47. M. Yamamoto, K. Agusa, K. Mase, H. Takada, N. Kawaguchi, H. Tomiyama, S. Honda, and N. Kaneko, "NEXCESS: Education for Embedded Software Specialists - Enhance Worker's Skill (in Japanese)," Journal of JSEE, vol. 54, no.5, pp. 49-54, Sep. 2006. [Free Download]
  48. M. Yamamoto, N. Kawaguchi, K. Agusa, K. Mase, H. Takada, H. Tomiyama, S. Honda, and N. Kaneko, "Remedial Education of Embedded Software Specialists for Working People (in Japanese)," IEEJ Trans. Fundamentals and Materials, vol. 126-A, no. 7, pp. 563-569, July 2006. [Download]
  49. H. Miyamoto, S. Iiyama, H. Tomiyama, H. Takada, and H. Nakashima, "A Search Algorithm of Worst-Case Cache Flush Timings Using Dynamic Programming (in Japanese)," IPSJ Trans. Advanced Computing Systems, vol. 46, no. SIG 16 (ACS12), pp. 85-94, Dec. 2005. [Free Download]
  50. M. Yamamoto, H. Tomiyama, H. Takada, K. Agusa, K. Mase, N. Kawaguchi, S. Honda, and N. Kaneko, "NEXCESS: Nagoya University Extension Courses for Embedded Software Specialists," ACM SIGBED Review, vol. 2, no. 4, pp. 20-24, Oct. 2005. [Download]
  51. H. Tomiyama, S. Chikada, S. Honda, and H. Takada, "An RTOS-Based Design and Validation Methodology for Embedded Systems," IEICE Trans. Information and Systems, vol. E88-D, no. 9, pp. 2205-2208, Sep. 2005. [Download]
  52. S. Honda, H. Tomiyama, and H. Takada, "SystemBuilder: A System Level Design Environment (in Japanese)," IEICE Trans. Information and Systems, vol. J88-D-I, no. 2, pp. 163-174, Feb. 2005. [Download]
  53. S. Honda, T. Wakabayashi, H. Tomiyama, and H. Takada, "RTOS-Centric Cosimulator for Embedded System Design," IEICE Trans. Fundamentals, vol. E87-A, no. 12, pp. 3030-3035, Dec. 2004. [Download]
  54. S. Iiyama, H. Tomiyama, H. Takada, M. Kido, and I. Hosotani, "Response Time Analysis for Grouped CAN Messages with Offsets (in Japanese)," IPSJ Trans. Advanced Computing Systems, vol. 45, no. SIG 11 (ACS 7), pp. 455-464, Oct. 2004. [Download]
  55. H. Tomiyama, "Impacts of Compiler Optimizations on Address Bus Energy: An Empirical Study," IEICE Trans. Fundamentals, vol. E87-A, no. 10, pp. 2815-2820, Oct. 2004. [Download]
  56. H. Tomiyama and N. Dutt, "ILP-Based Program Path Analysis for Bounding Worst-Case Inter-Task Cache Conflicts," IEICE Trans. Information and Systems, vol. E87-D, no. 6, pp. 1582-1587, June 2004. [Download]
  57. H. Tomiyama, H. Takada, and N. Dutt, "Memory Data Organization for Low-Energy Address Buses," IEICE Trans. Electronics, vol. E87-C, no. 4, pp. 606-612, Apr. 2004. [Download]
  58. P. Mishra, N. Dutt, and H. Tomiyama, "Towards Automatic Validation of Dynamic Behavior in Pipelined Processor Specifications," Kluwer Journal on Design Automation for Embedded Systems, vol. 8, no. 2-3, pp. 249-265, June-September, 2003.[Download]
  59. H. Tomiyama and H. Yasuura, "Module Selection Using Manufacturing Information," IEICE Trans. Fundamentals, vol. E81-A, no. 12, pp. 2576-2584, Dec. 1998. [Download]
  60. A. Inoue, H. Tomiyama, H. Okuma, H. Kanbara, and H. Yasuura, "Language and Compiler for Optimizing Datapath Widths of Embedded Systems," IEICE Trans. Fundamentals, vol. E81-A, no. 12, pp. 2595-2604, Dec. 1998. [Download]
  61. H. Tomiyama, T. Ishihara, A. Inoue, and H. Yasuura, "Instruction Scheduling to Reduce Switching Activity of Off-Chip Buses for Low-Power Systems with Caches," IEICE Trans. Fundamentals, vol. E81-A, no. 12, pp. 2621-2629, Dec. 1998. [Download]
  62. H. Yasuura, H. Tomiyama, A. Inoue, and F. N. Eko, "Embedded System Design Using Soft-Core Processor and Valen-C," IIS Journal of Information Science and Engineering, vol. 14, no. 3, pp. 587-603, Sep. 1998.
  63. F. N. Eko, A. Inoue, H. Tomiyama, and H. Yasuura, "Soft-Core Processor Architecture for Embedded System Design," IEICE Trans. Electronics, vol. E81-C, no. 9, 1416-1423, Sep. 1998. [Download]
  64. B. Shackleford, M. Yasuda, E. Okushi, H. Koizumi, H. Tomiyama, A. Inoue, and H. Yasuura, "Embedded System Cost Optimization via Data Path Width Adjustment," IEICE Trans. Information and Systems, vol. E80-D, no. 10, pp. 974-981, Oct. 1997. [Download]
  65. H. Tomiyama and H. Yasuura, "Code Placement Techniques for Cache Miss Rate Reduction," ACM Trans. Design Automation of Electronic Systems (TODAES), vol. 2, no. 4, pp. 410-429, Oct. 1997. [Download]
  66. B. Shackleford, M. Yasuda, E. Okushi, H. Koizumi, H. Tomiyama, and H. Yasuura, "Satsuki: An Integrated Processor Synthesis and Compiler Generation System," IEICE Trans. Information and Systems, vol. E79-D, no. 10, pp. 1373-1381, Oct. 1996. [Download]

Magazines and Technical Reports

  1. H. Tomiyama, "Hardware Technology for Embedded Systems (in Japanese)," Systems, Control and Information, no. 51, vol. 9, pp. 380-387, Sep. 2007.
  2. M. Yamamoto, K. Agusa, K. Mase, H. Takada, N. Kawaguchi, H. Tomiyama, S. Honda, and N. Kaneko, "Practice and Analysis of Extension Courses for Embedded Software Specialists in a University (in Japanese)," SEC journal, no. 1, vol. 4, pp. 36-45, Nov. 2005.
  3. H. Tomiyama and H. Yasuura, "Design Technology of Embedded Systems and its Research Trends (in Japanese)," IPSJ Magazine, vol. 40, no. 5, pp. 532-535, May 1999. [Free Download]
  4. H. Tomiyama, H. Akaboshi, and H. Yasuura, "Evaluation of Compiler Generator for Computer Architecture Evaluation (in Japanese)," Engineering Sciences Reports, Kyushu University, vol. 16, no. 3, pp. 339-344, Dec. 1994.